A schematic diagram of a binary rotator is shown in FIG. 1. This type of arrangement is known as a logarithmic rotator. The rotator 100 shown is for handling 16-bit words and has 16 inputs 102 and an array of 16 by 4 multiplexer units 104 connected as shown. There are 16 outputs 106 connected to the multiplexer outputs. The multiplexers are connected by possible paths shown in dashed lines, the actual connections that are operative at any moment being shown in heavy lines.
On the left hand side of FIG. 1 are the input bits of the binary number, bits 0 to 15. It is common in digital electronics to shift or to rotate the bits of a binary number for many different reasons and therefore these types of rotators are frequently provided.
The logarithmic rotator of FIG. 1 is implemented using a plurality of two-input or 2:1 multiplexer units. One of these is shown in more detail with reference to FIG. 2. In this, the unit has a pair of inputs A and B, an output C, and a control input S. The control input receives a logical 0 or a logical 1, and this determines the switching which takes place in the multiplexer to switch either the input from A or the input from B to the output C. Thus, when the control bit is a logical 0 input A is passed to the output C, as shown at (a) in FIG. 2, and when the control input is a logical 1, input B is switched to the output C, as shown at (b) in FIG. 2. For most of the multiplexers the output C is delivered to two subsequent multiplexers, and this is indicated at C1 and C2, though there are only 3 independent signal terminals.
Reverting to FIG. 1, it is seen that the multiplexers are in four banks. Starting from the input end, as shown, 16 multiplexers 104a receive at their A inputs a respective one of the inputs 102. At their inputs B they receive respectively the one of the inputs which is displaced by 8 input positions or bits from the input connected to their A input. Thus the first multiplexer 104a0 is connected to the 0 and 8 bit inputs, multiplexer 104a1 is connected to the 1 and 9 bit inputs, and so on to multiplexer 104a7 which is connected to the 7 and 15 bit inputs. Multiplexer 104a8 is then connected to the 8 and 0 inputs at its inputs A and B respectively, and this continues until finally multiplexer 104a15 is connected to the 15 and 7 bit inputs.
In the next bank 104b, the multiplexers are connected to the outputs of the multiplexers of the first bank 104a. They are somewhat similarly connected to the first bank but this time the two inputs A and B of any gate are connected to bits that are 4 apart rather than 8. Conversely, each multiplexer of the first bank is connected to two multiplexers of the second bank and this is why there are two signals C1 and C2 from each previous multiplexer. In the third bank 104c the inputs of any given gate are connected to the outputs of multiplexers of the second bank that are two bits apart, and in the fourth and final bank 104d the multiplexers are each connected to adjacent multiplexers of the third bank. The connections are clearly shown on FIG. 1 as will be well understood by those skilled in the art so a full detailed description in writing of all the possible connections is not necessary.
It is seen from the foregoing that the first multiplexer bank selectively provides for a rotation by 8 bits, the next bank by 4 bits, the third bank by 2 bits, and the final bank by 1 bit. Any desired rotation of 1 to 15 bits can be made from appropriate combination of the desired multiplexer banks.
It is the sequence 8, 4, 2, 1 that gives rise to the name ‘logarithmic’ rotator for this type of circuit. The rotator performs rotate operations by performing rotations by fixed powers of two in cascaded stages, selecting a rotating or non-rotating condition for each stage. In general, for a 2n-bit input there are n banks each of 2n multiplexers. The multiplexers of the first bank are connected to inputs 2n-1 input bits apart, the next to multiplexers of the first bank that are 2n-2 bits apart, and so on. The value of n will normally be 3, 4, or a larger integer.
With appropriate operation of the cascaded multiplexers, an input 16-bit number can be rotated by the circuit of FIG. 1 through any desired number of places. The way this is achieved will now be described. FIG. 1 shows the straight-through condition in which the input 102 is simply passed to the output 106 without any rotation.
Each multiplexer bank is fed a control input bit from control logic 108. The control inputs of each multiplexer of a bank are connected together; in fact the control bits are passed down the bank. The control logic 108 provides a four-bit output comprised of four control bits S3, S2, S1 and S0 in decreasing order of significance. In the FIG. 1 condition all four control bits are zero. Thus the A input of each one of the 64 multiplexers is selected.
In FIG. 1 all the four control bits are 0. If it is desired to rotate the input rather than pass it straight through, then the control bits are changed accordingly. In order to rotate by one bit, the bit S0 is changed from a 0 to a 1. To rotate by two bits, the bit S0 remains as a 0 but the control bit S1 is changed to a 1. To rotate by three bits, both control bits S0 and S1 are changed to a 1. Thus it is seen that the number of bits by which the input is to be rotated is simply set as the value represented by bits S3,S2,S1,S0.
FIG. 3 shows an example where a rotation by 5 bits is desired. Thus bits S0 and S2 are set to 1 while bits S1 and S3 remain at 0. The bits S3, S2, S1, S0 are thus binary 0101 and represent the digital value 5. Each multiplexer of the first and third banks 104a and 104c will select their A input, and each multiplexer of the second and fourth banks will select their B input. The consequential active connections are illustrated by heavy lines on FIG. 3, and it is seen that a 5-bit rotation does indeed result. More generally, using this arrangement enables an input bit to be shifted by up to fifteen logical positions within the input word. The connections along which the bits are shifted wrap around from position 0 to position 15, thereby enabling bits 0 to 15 to be shifted to any of the positions of bits 0 to 15 respectively using the appropriate control inputs to the multiplexers. A 4-bit word selects the amount of rotation to be implemented by the binary rotator.
Because the multiplexer components used in the arrangement shown in FIG. 1 are commonly available in a standard cell library, these type of rotating arrangements are relatively straightforward to design and implement and are commonly used. One example incorporating an arrangement along the lines of FIG. 1 is described in U.S. Pat. No. 5,991,786 to Mahurin.
Although the use of such circuits for effecting a rotation operation has been described above, similar arrangements can also be used to effect a shift. In this case the connections do not wrap around, but rather are terminated at the top edge of FIG. 1. To avoid undue complexity the description in this specification is given primarily in terms of rotation, but those skilled in the art will appreciate that with minor modification they can also be used for shifting operations.
Another useful operation that is frequently implemented in digital signal processing (DSP) hardware is the bit reverser function. In this, the most significant bit of an input word is exchanged with the least significant bit, the next most significant bit with the next least significant bit and so on such that the bits of the input word are reversed in the output word. When a function such as this has to be implemented continuously, all that is required is the rewiring of a data path. However, there are many applications where the bit reverse is an optional function. Thus, logical switching circuitry has to be used to enable the reversed or non-reversed form of the input word to be passed to the output. This function can be simply realised by using one column of two-input multiplexers and selecting between the bit-reversed or normal form of the bits.
FIG. 4 shows such a reverser that could be used in conjunction with a rotator if both rotation and reversing are desired as options. To reduce complexity an 8-bit input is shown (n=3) in this and the subsequent figures. The combined rotator/reverser shown in FIG. 4 includes a rotator based on FIG. 1 and is combined with a reverser formed of a further bank of two-input multiplexers 112. Each individual multiplexer 112-i is connected to receive a bit i and also the bit 7-i. That is, the first multiplexer 112-0 is connected to receive bits 0 and 7 from the output 106 of the rotator, the next multiplexer 112-1 is connected to receive bits 1 and 6, and so on.
The multiplexer bank 112 is controlled by a further control bit SR that is 0 if no reversal is required and is 1 if reversal is required. The control logic 118 can be extended to provide the control bit SR. When the control bit SR is 0, the upper input (as shown) of each multiplexer is selected, and when the control bit is 1, the lower input is selected.
It should be noted that FIG. 4 is not taken from any prior art document known to the applicant but is an illustration of a way in which both rotation and reversal could be provided using known techniques; however European Patent Application 264 130 (Fujitsu) describes a barrel shifter based on a rotator as described above that has a reverser section connected at its input and another reverser section connected at its output.
However, such an implementation would require a large number of wire crossings converging at a single point. This may cause wiring congestion in a silicon chip and this is undesirable. It would also require an increase in the number of multiplexer banks.
U.S. Pat. No. 6,675,182 to Hofstee et al. describes a rotator based on a logarithmic rotator but optimised to enable not only a normal rotate operation but also sub-field rotations. That is, for an 8-bit signal the upper and lower 4-bit components can each be selectively rotated, or adjacent pairs of bits can be selectively rotated. To achieve this, the multiplexer banks are not connected as shown in FIG. 1, 3 or 4 and described above, but rather are connected so as to swap bits which are 4, 2 and 1 bits apart respectively. The control logic used comprises fixed logic gates that require carry inputs from one multiplexer bank to the next.
A complicated structure for shifting and reordering two input 72-bit numbers using two banks of 16 and 8 eight-input gates connected through a matrix of busses, the gates of the 16-gate bank being independently controlled, is illustrated in U.S. Pat. No. 5,477,543 to Purcell. Further, no reversal arrangment is described.
Neither these nor any other prior art known to the applicant discloses an arrangement that enables selective rotation (or shifting) and/or reversal as desired using a minimum multiplexer configuration.